In recent years, significant progress has been realized in increasing the energy density for lithium ion batteries, nickel-hydrogen batteries and other batteries having relatively small capacities. As a result, with a small size and a light weight, the batteries can drive equipment for a long time. Improvements in the performance of batteries have significantly contributed to the popularization of portable electronic equipment, as represented by cell phones.
Also, with improvements in the performance of the battery itself, the performance of peripheral circuits has also improved. For example, notebook computers, camcorders, and other electronic equipment that allow exchange of batteries carry a type of battery device (also known as battery pack) having an electronic circuit that can realize a remaining charge management function and other functions and is incorporated in the battery main body. Recently, battery devices that can realize said functions by means of microcomputers (hereinafter to be referred to as “μC”) have become popular.
On the other hand, for lithium batteries and other high-performance batteries, overcharging may lead to an abnormally high cell voltage, overdischarge may lead to too low a cell voltage, or, when an excessive charge/discharge current flows in the cell, degradation in characteristics and problems may readily take place in the structure. This is undesired. Consequently, a conventional battery device carries a circuit that can cut off the power feeding path between the battery and the electronic equipment to protect the battery when said abnormal charge/discharge takes place.
In order to cut off the power feeding path, usually, transistors or other semiconductor switching elements are used. For example, one may use a power MOSFET that has a low ON resistance and allows driving at a high current. Japanese Kokai Patent Application No. Hei 11[1999]-187578 describes a type of battery protecting circuit that cuts the power feeding path on the side of the positive electrode of the battery by means of an n-channel MOS transistor.
FIG. 10 is a diagram illustrating an example of the constitution of a battery device having a protecting circuit that cuts off the power feeding path on the side of the positive electrode of the battery by means of an n-channel MOS transistor (hereinafter to be referred to as “NMOS transistor”). As shown in FIG. 10, battery device 100 has NMOS transistors Q1, Q2, battery B1, resistor Rs1, protecting circuit 101, and microcomputer 102. For example, said battery (secondary battery) B1 is composed of plural lithium ion batteries or other battery cells connected in series. In the example shown in FIG. 10, three battery cells CEL1-CEL3 are connected in series.
NMOS transistors Q1 and Q2 have their drains connected in common. The source of NMOS transistor Q1 is connected to positive electrode PACK+ of battery device 100. The source of NMOS transistor Q2 is connected to positive electrode BAT+ of battery B1. Resistor Rs1 is connected between negative electrode BAT− of battery B1 and negative electrode PACK− of battery device 100. Said resistor Rs1 is used to detect the charge/discharge current of battery B1 in microcomputer 102 and protecting circuit 101.
Said protecting circuit 101 generates driving voltages fed to the gates of NMOS transistors Q1, Q2, and switches them ON/OFF. For example, it communicates with microcomputer 102 via a prescribed interface, and stores a set value sent from microcomputer 102 in an internal register. Then, according to the set value stored in the register, it switches ON/OFF NMOS transistors Q1, Q2.
Also, protecting circuit 101 contains a boosting circuit made of charge pump circuit or the like for generating the driving voltage of NMOS transistors Q1, Q2. The boosting circuit that generates the driving voltage of NMOS transistor Q1 boosts the voltage generated at the source (that is, positive electrode PACK+) of NMOS transistor Q1, and feeds it to the gate of NMOS transistor Q1. The boosting circuit that generates the driving voltage of NMOS transistor Q2 boosts the voltage generated at the source (that is, positive electrode BAT+) of NMOS transistor Q2 and feeds it to the gate of NMOS transistor Q2.
In addition, protecting circuit 101 contains a power source circuit for feeding power source voltage Vreg to an internal circuit and external microcomputer 102. For example, this power source circuit is composed of a linear regulator of low-dropout, and it lowers voltage VDD generated at the common drain of NMOS transistors Q1, Q2 to generate a prescribed-level power source voltage Vreg.
Also, protecting circuit 101 has several functions, such as a function with which the charging current of battery B1 is monitored based on the voltage generated across resistor Rs1, and NMOS transistors Q1, Q2 are cut off if an overcurrent is detected, and a function that detects the voltage of the battery cells CEL1-CEL3 selected corresponding to the set value of the register, and it is output to microcomputer 102.
Said microcomputer 102 monitors the charge/discharge current of battery B1 and the voltages of the various cells. If abnormality takes place, such as overcharging, overdischarge, overcurrent, etc., the set value is written in the register of protecting circuit 101 so that NMOS transistors Q1, Q2 are turned OFF. Also, it performs a treatment in which the charge/discharge current of battery B1 is integrated and the remaining charge in the battery is predicted, and a treatment in which the threshold for detection of overcurrent is set in protecting circuit 101.
Also, microcomputer 102 communicates with electronic equipment 200 to be explained later by means of an SMBUS (system management bus) or another interchip interface, and provides the information of the remaining charge of the battery of battery device 100 to electronic equipment 200.
Said battery device 100 is connected to electronic equipment 200, such as a personal computer or the like, for use. For example, as shown in FIG. 10, electronic equipment 200 has charging circuits CH1, CH2, switching circuits SW1, SW2, microcomputer 210, and load 220.
Load 220 represents the internal load of working electronic equipment 200 when power is fed from battery device 100. Charging circuits CH1, CH2 generate charging currents I1, I2 for charging battery device 100, and they are output to the power feeding path on the positive electrode PACK+ side of battery device 100. Charging circuit CH1 is connected via switching circuit SW1 to the power feeding path, and, when switching circuit SW1 is ON, charging current I1 is output to the power feeding path.
Said charging circuit CH2 is connected via switching circuit SW2 to the power feeding path, and, when switching circuit SW2 is ON, charging current I2 is output to the power feeding path. Said charging circuit CH1 is used in the normal charging operation of battery device 100. On the other hand, charging circuit CH2 is used for preparatory charging (precharging) when the battery voltage is below a prescribed level. Charging current I2 output from charging circuit CH2 is smaller than charging current I1 output from charging circuit CH1.
Said microcomputer 210 communicates with microcomputer 102 of battery device 100 by means of an SMBUS or the like, and it acquires the remaining charge of the battery and other information. Also, based on the information acquired from battery device 100, charging circuits CH1, CH2 and switching circuits SW1, SW2 are controlled, and the charging current of battery B1 is set at an appropriate value.
In the following, with reference to FIG. 11, an explanation will be given regarding the charging operation when the battery voltage falls nearly to zero volts due to overdischarge or the like in said battery device 100 shown in FIG. 10.
When the battery voltage falls nearly to zero volts, in order to avoid damage to the battery cells due to excessive charging current, battery B1 is charged by precharging current (I2), smaller than normal current (I1).    Step ST1:
The voltage of battery B1 is at zero volts, and switching circuit SW2 is set ON, so that precharging is started with charging current I2.    Step ST2:
In this case, because both NMOS transistors Q1, Q2 of battery device 100 are OFF, charging current Ipack fed to positive electrode PACK+ flows via body diode D1 of NMOS transistor Q1 to the drain of NMOS transistor Q1, so that voltage VDD rises (FIG. 11(A)).    Step ST3:
Due to the rise in voltage VDD, the power source circuit of protecting circuit 101 starts working, and when power source voltage Vreg is generated, said power source voltage Vreg is received, and the operation of the boosting circuit of protecting circuit 101 starts. Also, by means of said power source voltage Vreg, protecting circuit 101 is started (FIG. 11(D)).    Step ST4:
Due to the driving voltage generated by the boosting circuit, NMOS transistor Q2 is turned ON, and charging current Ipack (=I2) flows to batteries CEL1-CEL3 (FIG. 11(C)).    Step ST5:
When the voltage of the driving voltage of the boosting circuit rises, the ON resistances of NMOS transistors Q1, Q2 decrease, so that voltage VDD falls.    Step ST6:
When the voltage of voltage VDD falls below the voltage at which the power source circuit can work, feeding of power source voltage Vreg from the power source circuit is stopped, and the operation of the boosting circuit is stopped. As a result, NMOS transistor Q2 is turned OFF, and the charging current of battery B1 becomes zero (FIG. 11(C)). Also, because the feeding of power source voltage Vreg is stopped, protecting circuit 101 is shut down (FIG. 11(D)).    Step ST7:
When NMOS transistor Q2 is turned OFF, voltage VDD rises again due to charging current Ipack that flows via body diode D1. Until the voltage of battery B1 reaches a voltage that allows working of the power source circuit, the operation of said steps ST2-ST6 is repeated, and the battery is charged intermittently.    Step ST8:
When the voltage of battery B1 reaches a prescribed level at which the power source circuit can work, even if NMOS transistor Q2 is ON, the power source circuit is still not stopped. As a result, the boosting circuit keeps working, and NMOS transistor Q2 is kept ON as is. Consequently, the battery is charged by a constant charging current Ipack (=I2).    Step ST9:
The voltage of battery B1 further rises, and when it reaches the level at which charging can be performed with the normal charging current, switching circuit SW2 is turned OFF and switching circuit SW1 is turned ON, and charging current I1 is fed to the battery (FIG. 11(C)). Also, both NMOS transistors Q1, Q2 are turned ON. As a result, charging is performed at a rate higher than that in the precharging mode.    Step ST10:
When the voltage of battery B1 reaches the upper limit value (Vc) of the output voltage of charging circuit CH1, charging current I1 becomes zero, and charging of battery B1 comes to an end.
In this way, in battery device 100 shown in FIG. 10, when the battery voltage falls nearly to zero volts due to overdischarge or the like, the boosting circuit of battery device 100 cannot stably operate, and NMOS transistor Q2 is turned ON/OFF alternately. Consequently, the charging current flowing to the battery becomes intermittent, and this is undesired. Especially when NMOS transistor Q2 changes from OFF to ON, the current flowing to the battery may temporarily become higher than precharging current I2, and this may lead to degradation of the battery cells.
A general object of the present invention is to solve the aforementioned problems of the prior art by providing a type of battery protecting circuit characterized by the fact that by means of a driving voltage generated by boosting the voltage generated in the power feeding path between the external power source and the battery, the NMOS transistor or other switching circuit set in the power feeding path is switched ON/OFF, and even when the battery voltage falls nearly to zero volts due to overdischarge or the like, the battery can still be charged steadily with a constant charging current.